| Assembleur SuperH | STS |
|---|---|
| SuperH | Store System Register |
Syntaxe
| STS MACH,Rn |
| STS MACL,Rn |
| STS PR,Rn |
| STS DSR,Rn |
| STS A0,Rn |
| STS X0,Rn |
| STS X1,Rn |
| STS Y0,Rn |
| STS Y1,Rn |
| STS.L MACH,@-Rn |
| STS.L MACL,@-Rn |
| STS.L PR,@-Rn |
| STS.L DSR,@-Rn |
| STS.L A0,@-Rn |
| STS.L X0,@-Rn |
| STS.L X1,@-Rn |
| STS.L Y0,@-Rn |
| STS.L Y1,@-Rn |
Description
Cette instruction permet d'entreposer les données du registre système MACH, MACL ou PR ou le registre DSP, DSR, A0, X0, X1, Y0 ou Y1 dans la destination spécifié.
Algorithme
|
MODULE STSMACH(n) * STS MACH,Rn R[n] ← MACH SI R[n] ∩ 00000200h = 0 ALORS R[n] ← R[n] ∩ 000003FFh SINON R[n] ← R[n] U FFFFFC00h FIN SI PC ← PC + 2 MODULE STSMACL(n) * STS MACL,Rn R[n] ← MACL PC ← PC + 2 MODULE STSPR(n) * STS PR,Rn R[n] ← PR PC ← PC + 2 MODULE STSDSR(n) * STS DSR,Rn R[n] ← DSR PC ← PC + 2 MODULE STSA0(n) * STS A0,Rn R[n] ← A0 PC ← PC + 2 MODULE STSX0(n) * STS X0,Rn R[n] ← X0 PC ← PC + 2 MODULE STSX1(n) * STS X1,Rn R[n] ← X1 PC ← PC + 2 MODULE STSY0(n) * STS Y0,Rn R[n] ← Y0 PC ← PC + 2 MODULE STSY1(n) * STS Y1,Rn R[n] ← Y1 PC ← PC + 2 MODULE STSMMACH(n) * STS.L MACH,@-Rn R[n] ← R[n] - 4 SI MACH ∩ 00000200h = 0 ALORS Write_Long(R[n],MACH ∩ 000003FFh) SINON Write_Long(R[n],MACH U FFFFFC00h) FIN SI Write_Long(R[n], MACH) PC ← PC + 2 MODULE STSMMACL(n) * STS.L MACL,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],MACL) PC ← PC + 2 MODULE STSMPR(n) STS.L PR,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],PR) PC ← PC + 2 MODULE STSMDSR(n) * STS.L DSR,@-R R[n] ← R[n] - 4 Write_Long(R[n],DSR) PC ← PC + 2 MODULE STSMA0(n) * STS.L A0,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],A0) PC ← PC + 2 MODULE STSMX0(n) * STS.L X0,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],X0) PC ← PC + 2 MODULE STSMX1(n) * STS.L X1,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],X1) PC ← PC + 2 MODULE STSMY0(n) * STS.L Y0,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],Y0) PC ← PC + 2 MODULE STSMY1(n) * STS.L Y1,@-Rn R[n] ← R[n] - 4 Write_Long(R[n],Y1) PC ← PC + 2 |
Mnémonique
| Instruction | Abstrait | Opcode | Cycle |
|---|---|---|---|
| STS MACH,Rn | Rn ← MACH | 0000nnnn00001010 | 1 |
| STS MACL,Rn | Rn ← MACL | 0000nnnn00011010 | 1 |
| STS PR,Rn | Rn ← PR | 0000nnnn00101010 | 1 |
| STS DSR,Rn | Rn ← DSR | 0000nnnn01101010 | 1 |
| STS A0,Rn | Rn ← A0 | 0000nnnn01111010 | 1 |
| STS X0,Rn | Rn ← X0 | 0000nnnn1000101 | 1 |
| STS X1,Rn | Rn ← X1 | 0000nnnn1001101 | 1 |
| STS Y0,Rn | Rn ← Y0 | 0000nnnn1010101 | 1 |
| STS Y1,Rn | Rn ← Y1 | 0000nnnn1011101 | 1 |
| STS.L MACH,@-Rn | Rn ← Rn - 4, (Rn) ← MACH | 0100nnnn00000010 | 1 |
| STS.L MACL,@-Rn | Rn ← Rn - 4, (Rn) ← MACL | 0100nnnn00010010 | 1 |
| STS.L PR,@-Rn | Rn ← Rn - 4, (Rn) ← PR | 0100nnnn00100010 | 1 |
| STS.L DSR,@-Rn | Rn ← Rn - 4, (Rn) ← DSR | 0100nnnn01100010 | 1 |
| STS.L A0,@-Rn | Rn ← Rn - 4, (Rn) ← A0 | 0100nnnn01100010 | 1 |
| STS.L X0,@-Rn | Rn ← Rn - 4, (Rn) ← X0 | 0100nnnn1000001 | 1 |
| STS.L X1,@-Rn | Rn ← Rn - 4, (Rn) ← X1 | 0100nnnn1001001 | 1 |
| STS.L Y0,@-Rn | Rn ← Rn - 4,(Rn) ← Y0 | 0100nnnn1010001 | 1 |
| STS.L Y1,@-Rn | Rn ← Rn - 4,(Rn) ← Y1 | 0100nnnn1011001 | 1 |
Dernière mise à jour : Mardi, le 28 juillet 2015